Standard cell libraries are used to ease the design and the synthesis of integrated circuits. Each cell corresponds to an elementary component (for example, a MOS transistor) or to an assembly of components performing a function (for example, an OR, AND, NOR, or NAND gate, an inverter, a pair of transistors, an elementary amplifier, etc.). A library contains a set of parameters defining the circuit design and the topology, as well as the input and output terminals of each cell. Each cell is further defined by parameters such as a response time, an output power, etc. In the synthesis of an integrated circuit, cells of the library are selected, arranged, and interconnected, to provide the required circuit functions.
FIG. 1A is a top view very schematically showing an elementary cell 1 containing a single MOS transistor.
FIG. 1B is a cross-section view along plane B-B of cell 1 of FIG. 1A.
The MOS transistor of cell 1, formed in the upper portion of a P-type semiconductor substrate, comprises an N+-type source region 3, and an N+-type drain region 5, located on either side of a gate 7 isolated from the substrate by an insulating layer 9. N-type regions 11 and 13, more lightly doped than regions 3 and 5, are formed in the upper portion of the substrate under insulating spacers 15 and 16. Gate 7 has a length L and a width W. Gate 7 is for example made of polysilicon and has, in top view, the shape of a rectangular strip. Source and drain regions 3 and 5 are generally covered with a silicide contacting layer. The entire cell is delimited by insulating trenches 19 filled with an insulator, for example, silicon oxide, currently designated as STI, for “Shallow Trench Isolation”. Vias 21 and 23 come into contact with silicide regions 17 at the level of contact areas 22 and 24, and enable forming electric connections with source and drain regions 3 and 5. Contact areas 22 and 24 are arranged, in top view, substantially at the center of the source and drain regions.
In the case where the MOS transistor of cell 1 must be a transistor of minimum dimensions in the considered technology, the library especially defines that:                the gate length Lmin of the transistor is the minimum gate length that can be achieved in the considered technology, for example, on the order of 40 nm; and        distances dGSmin between gate 7 and source contact area 22 and dGDmin between gate 7 and drain contact area 24 are the smallest distances that can be achieved in the considered technology without any risk of short-circuit between the gates and the contact areas, for example, also on the order of 40 nm.        
This enables one to obtain a maximum operating speed of the transistor and a minimum silicon surface area consumption.
FIG. 1C is a top view schematically showing another standard cell 31 of the library. Cell 31 comprises two MOS transistors sharing their source-drain. Contact areas 32 and 34 are provided on the side of the non-common drain and source regions of the cell. Cell 31 comprises two parallel gates 37 and 39, of same length Lmin and of same width W. Gates 37 and 39 are arranged between contact areas 32 and 34. The entire cell is delimited by isolation trenches 40. As in cell 1 of FIGS. 1A and 1B, the transistors of cell 31 are made at the minimum dimensions of the selected manufacturing technology. In this case, in addition to the minimum distance between the contact areas and the gates, a minimum distance dGGmin must be respected between the two gates to avoid any risk of short-circuit. Distance dGGmin is for example on the order of 140 nm in 40-nm CMOS technology (the drawing is not to scale).
A disadvantage of MOS transistors of minimum dimensions, and thus of maximum operating speed, is that such transistors have relatively high leakage currents. Indeed, the shorter the gate length of a MOS transistor, the larger the leakage current that it conducts in the off state. This results in an increase of the integrated circuit consumption. For certain transistors of an integrated circuit, the operating speed is not a critical parameter. It is thus unnecessary for such transistors to use cells resulting in high leakage currents.
An obvious solution is to define, in the library, additional cells in which the MOS transistors have a gate length greater than the minimum gate length of the technology. Thus, to form a same component, the designer may, during the synthesis, choose between two cells according to whether he wishes to optimize the transistor operating speed or the electric consumption.
However, increasing the gate length of the transistors implies increasing the surface area taken up by the cell, especially to respect the minimum guard distance between the gate(s) and the source and drain contact areas. Thus, for a same component, the library would define two cells of different sizes, the smaller one being characterized by a higher operating speed of the transistors, and the larger one by a lower electric consumption. In addition to the cost in silicon surface area directly resulting from the increase of the dimensions of certain cells, such a solution has the disadvantage of making the integrated circuit synthesis process more difficult. Indeed, the increase of the number of cells of different sizes in the library causes location and interconnection issues. This especially results in losses in useful silicon surface area.